This invention relates to clock recovery apparatus for decoding or retiming binary data and, more particularly, to improvements in a phase locked loop for clock recovery.
U.S. Pat. No. 5,012,494 discloses a phase locked loop architecture for clock recovery and NRZ data retiming. A clock signal generated by a voltage controlled oscillator (VCO) is compared with the NRZ data in a frequency/phase detector. The frequency/phase detector has a binary output that serves as an error signal for the phase locked loop. The output of the frequency/phase detector is one binary value when the clock signal leads the data transitions and is the other binary value when the clock signal lags the data transitions. The output of the frequency/phase detector is directly connected to the VCO to make small first order corrections in its phase and is connected through an integrator to the VCO to make larger second order corrections to its frequency. In the frequency acquisition mode, the second order corrections bring the clock signal into frequency synchronization and phase lock with the data transitions. In the phase lock mode, the first order corrections cause the frequency of the clock signal to shift slightly back and forth, i.e., toggle, about the frequency of the data transitions, and thereby maintain phase lock.
The described phase locked loop architecture only corrects the frequency and phase of the clock signal when data transitions are present. Therefore, during long strings of data having the same binary value, the clock frequency can drift, which gives rise to pattern dependent jitter.
A false lock condition can also arise in the described phase locked loop architecture when the data transition and clock signal frequencies are fractionally related. In such case, although correct phase lock to data is absent with the data transitions and the clock signal in phase every several clock cycles, this may "fool" the phase lock circuitry into "thinking" it is in correct phase lock.
In the referenced patent, the VCO comprises a plurality of stages of delay connected in a ring. One of the stages introduces a binary delay depending upon the binary value of the directly applied signal from the frequency/phase detector. Each time the output of the frequency/phase detector changes state, the binary delay changes and the frequency of the VCO toggles back and forth between two values. The remaining stages each introduce an analog delay depending on the output of the integrator, as the loop approaches phase lock. Over temperature, differing analog delays are introduced by the stages, and thus the frequency range of the VCO changes appreciably as a function of temperature. This can cause the phase locked loop to operate improperly.